WestminsterResearch

Accelerating JPEG compression with a dynamically reconfigurable FPGA systolic array

Cadenas, Oswaldo and Megson, Graham M. and Plaks, Toomas P. (2000) Accelerating JPEG compression with a dynamically reconfigurable FPGA systolic array. In: International Conference on Parallel and Distibuted Processing Techniques and Applications, vol VI, 26 - 29 June 2000, Las Vegas, USA. (Submitted)

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Item Type:Conference or Workshop Item (Paper)
Research Community:University of Westminster > Electronics and Computer Science, School of
ID Code:10234
Deposited On:02 Feb 2012 10:39
Last Modified:02 Feb 2012 10:39

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