C-slow retimed parallel histogram architectures for consumer imaging devices

Cadenas, José, Sherratt, R. Simon, Huerta, Pablo, Wen-Chung, Kao and Megson, Graham M. (2013) C-slow retimed parallel histogram architectures for consumer imaging devices. IEEE Transactions on Consumer Electronics, 59 (2). pp. 291-295. ISSN 0098-3063

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Official URL: http://dx.doi.org/10.1109/TCE.2013.6531108


A parallel pipelined array of cells suitable for real-time computation of histograms is proposed. The cell architecture builds on previous work obtained via C-slow retiming techniques and can be clocked at 65 percent faster frequency than previous arrays. The new arrays can be exploited for higher throughput particularly when dual data rate sampling techniques are used to operate on single streams of data from image sensors. In this way, the new cell operates on a p-bit data bus which is more convenient for interfacing to camera sensors or to microprocessors in consumer digital cameras.

Item Type: Article
Subjects: University of Westminster > Science and Technology > Electronics and Computer Science, School of (No longer in use)
Depositing User: Miss Nina Watts
Date Deposited: 23 Jul 2013 11:24
Last Modified: 23 Jul 2013 11:24
URI: http://westminsterresearch.wmin.ac.uk/id/eprint/12763

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