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Improving the performance of Morton layout by array alignment and loop unrolling: reducing the price of naivety

Thiyagalingam, Jeyarajan and Beckmann, Olav and Kelly, Paul H.J. (2003) Improving the performance of Morton layout by array alignment and loop unrolling: reducing the price of naivety. In: Rauchwerger, Lawrence, (ed.) Languages and Compilers for Parallel Computing: 16th International Workshop, LCPC 2003, College Station, TX, USA, October 2-4, 2003: revised papers. Lecture notes in computer science (2958). Springer, London, UK, pp. 241-257. ISBN 3540211993

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Official URL: http://dx.doi.org/10.1007/b95707

Abstract

Hierarchically-blocked non-linear storage layouts, such as the Morton ordering, have been proposed as a compromise between row-major and column-major for two-dimensional arrays. Morton layout offers some spatial locality whether traversed row-wise or column-wise. The goal of this paper is to make this an attractive compromise, offering close to the performance of row-major traversal of row-major layout, while avoiding the pathological behaviour of column-major traversal. We explore how spatial locality of Morton layout depends on the alignment of the arrays base address, and how unrolling has to be aligned to reduce address calculation overhead. We conclude with extensive experimental results using five common processors and a small suite of benchmark kernels.

Item Type:Book Section
Research Community:University of Westminster > Electronics and Computer Science, School of
ID Code:1495
Deposited On:08 May 2006
Last Modified:19 Oct 2009 16:10

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