A high-speed, low-power interleaved trace-back memory for Viterbi decoder

Israsena, Pasin and Kale, Izzet (2006) A high-speed, low-power interleaved trace-back memory for Viterbi decoder. In: 2006 IEEE International Symposium on Circuits and Systems. ISCAS 2006. Proceedings. IEEE, Los Alamitos, USA, pp. 2801-2804. ISBN 0780393902


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Official URL: http://dx.doi.org/10.1109/ISCAS.2006.1693206


This paper presents a high-speed, low-power trace-back memory structure for a Viterbi decoder. The new memory is based on an array of registers connected with trace-back signals that decode the output bits on the fly. The trace-back memory is internally interleaved such that high-speed characteristic is achieved while low-power consumption is maintained. The structure is used together with appropriate clock and power-aware control signals. The design is 100% portable and is suitable for a SoftIP approach. Based on the AMS 0.35 /spl mu/m CMOS implementation the trace-back memory is estimated to consume energy of 232 pJ, which is 53.6% less than a conventional RAM based design, with a maximum throughput of 1.1 Gbps.

Item Type: Book Section
Uncontrolled Keywords: CMOS memory circuits, Viterbi decoding, interleaved storage, low-power electronics, 0.35 micron, 1.1 Gbit/s 232 pJ, AMS CMOS, SoftIP approach, Viterbi decoder, clock signal, high-speed characteristic, low-power consumption, power-aware control signals, registers array, trace-back memory
Subjects: University of Westminster > Science and Technology > Electronics and Computer Science, School of (No longer in use)
Depositing User: Miss Nina Watts
Date Deposited: 19 Feb 2007
Last Modified: 11 Aug 2010 14:31
URI: http://westminsterresearch.wmin.ac.uk/id/eprint/3337

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