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Continuous time delta sigma modulators with reduced clock jitter sensitivity

Zare-Hoseini, Hashem and Kale, Izzet (2006) Continuous time delta sigma modulators with reduced clock jitter sensitivity. In: 2006 IEEE International Symposium on Circuits and Systems. ISCAS 2006. Proceedings. IEEE, Los Alamitos, USA, pp. 5371-5374. ISBN 0780393902


Official URL: http://dx.doi.org/10.1109/ISCAS.2006.1693847


In this paper, a technique and method is presented to suppress the effect of clock-jitter in continuous-time delta-sigma modulators with switched-current (current-steering) digital to analogue converters. A behavioural, transistor-level and noise analysis are presented followed by circuit-level simulations. The proposed approach which is a switched-current type of digital to analogue conversion is fully compatible with CMOS processes and multi-bit operations which are widely used in high speed applications. Moreover, having a pulse-shaped output signal does not introduce extra demands on the modulator and hence does not increase the modulator's power consumption. A third-order continuous-time /spl Delta//spl Sigma/ modulator with the proposed digital-to-analogue converter in its feedback was used for circuit-level simulations. Results proved the robustness of the technique in suppressing the clock-jitter effects.

Item Type:Book Section
Uncontrolled Keywords:CMOS integrated circuits, circuit simulation, clocks, continuous time systems, delta-sigma modulation, jitter switched current circuits, CMOS process, behavioural analysis, circuit-level simulations, clock jitter sensitivity, continuous time modulators, current-steering digital to analogue converters, delta sigma modulators noise analysis, switched-current digital to analogue converters, transistor-level
Research Community:University of Westminster > Electronics and Computer Science, School of
ID Code:3338
Deposited On:19 Feb 2007
Last Modified:11 Aug 2010 15:31

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