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A new structure for capacitor-mismatch-insensitive multiply-by-two amplification

Zare-Hoseini, Hashem and Shoaei, Omid and Kale, Izzet (2006) A new structure for capacitor-mismatch-insensitive multiply-by-two amplification. In: 2006 IEEE International Symposium on Circuits and Systems. ISCAS 2006. Proceedings. IEEE, Los Alamitos, USA, pp. 4879-4882. ISBN 0780393902


Official URL: http://dx.doi.org/10.1109/ISCAS.2006.1693724


A new approach to achieve a switched-capacitor multiply-by-two gain-stage with reduced sensitivity to capacitors' mismatches is presented in this paper. It is based on sampling fully differential input signals onto both plates of the input capacitors rather than sampling onto one plate of the capacitors with the other tied to a reference. It uses one operational amplifier (op-amp) in two phases to produce the gain of two (/spl times/2). Comparing to the conventional multiply-by-two gain-stage, the mismatches between the capacitors has a much smaller influence on the accuracy of the gain of two (/spl times/2). Analytical and circuit-level analysis of the architecture and the conventional structure are presented using a generic 0.35/spl mu/m CMOS technology.

Item Type:Book Section
Uncontrolled Keywords:CMOS integrated circuits, analogue-digital conversion, network analysis, operational amplifiers, switched capacitor networks, 0.35 micron, CMOS technology, analog-to-digital converters, capacitor mismatch, circuit level analysis, input capacitors, multiply-by-two amplification, operational amplifier, switched capacitor
Research Community:University of Westminster > Electronics and Computer Science, School of
ID Code:3339
Deposited On:19 Feb 2007
Last Modified:11 Aug 2010 15:31

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