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A Viterbi decoder with low-power trace-back memory structure for wireless pervasive communications

Israsena, Pasin and Kale, Izzet (2006) A Viterbi decoder with low-power trace-back memory structure for wireless pervasive communications. In: 1st International Symposium on Wireless Pervasive Computing, 2006. IEEE, Los Alamitos, USA. ISBN 0780394100

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Official URL: http://dx.doi.org/10.1109/ISWPC.2006.1613572

Abstract

This paper presents a new trace-back memory structure for Viterbi decoders that reduces power consumption by 63% compared to the conventional RAM based design. Instead of the intensive read and write operations as required in RAM based designs, the new memory is based on an array of registers connected with trace-back signals that decode the output bits on the fly. The structure is used together with appropriate clock and power-aware control signals. Based on a 0.35 /spl mu/m CMOS implementation the trace-back back memory consumes energy of 182 pJ.

Item Type:Book Section
Uncontrolled Keywords:CMOS integrated circuits, Viterbi decoding, mobile radio, random-access storage, 182 pJ, CMOS implementation, RAM based design, Viterbi decoder, clock control signals, low-power trace-back memory structure, power consumption power-aware control signals, register array, trace-back signals, wireless pervasive communications
Research Community:University of Westminster > Electronics and Computer Science, School of
ID Code:3341
Deposited On:19 Feb 2007
Last Modified:11 Aug 2010 15:31

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