Zare-Hoseini, Hashem and Kale, Izzet and Shoaei, Omid (2005) Modeling of switched-capacitor delta-sigma Modulators in SIMULINK. IEEE Transactions on Instrumentation and Measurement, 54 (4). pp. 1646-1654. ISSN 0018-9456
Official URL: http://dx.doi.org/10.1109/TIM.2005.851085
Precise behavioral modeling of switched-capacitor /spl Delta//spl Sigma/ modulators is presented. Considering noise (switches' and op-amps' thermal noise), clock jitter, nonidealities of integrators and op-amps including finite dc-gain (DCG) and unity gain bandwidth, slew-limiting, DCG nonlinearities and the input parasitic capacitance, quantizer hysteresis, switches' clock-feedthrough, and charge injection, exhaustive behavioral simulations that are close models of the transistor-level ones can be performed. The DCG nonlinearity of the integrators, which is not considered in many /spl Delta//spl Sigma/ modulators' modeling attempts, is analyzed, estimated, and modeled. It is shown that neglecting this parameter would lead to a significant underestimation of the modulators' behavior and increase the noise floor as well as the harmonic distortion at the output of the modulator. Evaluation and validation of the models were done via behavioral and transistor-level simulations for a second-order modulator using SIMULINK and HSPICE with a generic 0.35-/spl mu/m CMOS technology. The effects of the nonidealities and nonlinearities are clearly seen when compared to the ideal modulator in the behavioral and actual modulator in the circuit-level environment.
|Uncontrolled Keywords:||CMOS digital integrated circuits, circuit simulation, delta-sigma modulation, integrated circuit modelling integrated circuit noise, jitter, switched capacitor networks, 0.35 micron, CMOS digital integrated circuits DCG integrator nonlinearity, SIMULINK, behavioral modeling, behavioral simulation, circuit simulation, clock jitter, integrated circuit modeling, integrated circuit noise, switched-capacitor /spl Delta//spl Sigma/ modulators, switched-capacitor delta-sigma modulators, transistor-level simulation|
|Research Community:||University of Westminster > Electronics and Computer Science, School of|
|Deposited On:||29 Jun 2007|
|Last Modified:||11 Aug 2010 15:32|
Repository Staff Only: item control page