Bland, Ian M. and Megson, Graham M. (1997) Efficient operator pipelining in a bit serial genetic algorithm engine. Electronics Letters, 33 (12). pp. 1026-1028. ISSN 0013-5194Full text not available from this repository.
The authors propose a bit serial pipeline used to perform the genetic operators in a hardware genetic algorithm. The bit-serial nature of the dataflow allows the operators to be pipelined, resulting in an architecture which is area efficient, easily scaled and is independent of the lengths of the chromosomes. An FPGA implementation of the device achieves a throughput of >25 million genes per second.
|Uncontrolled Keywords:||Field programmable gate arrays, genetic algorithms, pipeline processing, systolic arrays, FPGA implementation architecture, bit serial genetic algorithm engine, bit serial pipeline, operator pipelining|
|Subjects:||University of Westminster > Science and Technology > Electronics and Computer Science, School of (No longer in use)|
|Depositing User:||Miss Nina Watts|
|Date Deposited:||27 Jan 2009 11:01|
|Last Modified:||19 Oct 2009 11:24|
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