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Scalar quantisation using a fast systolic array

Megson, Graham M. and Diemoz, E. (1997) Scalar quantisation using a fast systolic array. Electronics Letters, 33 (17). pp. 1435-1437. ISSN 0013-5194

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Official URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumbe...

Abstract

A systolic array capable of outperforming a table look-up quantiser is proposed. The design has high throughput, can perform uniform or non-uniform quantisation and is suitable for VLSI or field programmable gate array (FPGA) implementation. In the latter case, the array can be used dynamically to both reduce latency and switch between quantisers without the need to reset look-up tables.

Item Type:Article
Uncontrolled Keywords:VLSI, data compression, field programmable gate arrays, quantisation (signal), systolic arrays, FPGA implementation, VLSI implementation fast systolic array, field programmable gate array, high throughput, nonuniform quantisation, scalar quantisation, uniform quantisation
Research Community:University of Westminster > Electronics and Computer Science, School of
ID Code:5704
Deposited On:27 Jan 2009 11:06
Last Modified:19 Oct 2009 16:49

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