Bland, Ian M. and Megson, Graham M. (1996) Systolic random number generation for genetic algorithms. Electronics Letters, 32 (12). pp. 1069-1070. ISSN 0013-5194Full text not available from this repository.
A parallel hardware random number generator for use with a VLSI genetic algorithm (GA) processing device is proposed. The design uses a systolic array of mixed congruential random number generators. The generators are constantly reseeded with the outputs of the proceeding generators to avoid significant biasing of the randomness of the array, which would result in longer times for the algorithm to converge to a solution.
|Uncontrolled Keywords:||VLSI, genetic algorithms, random number generation systolic arrays, VLSI processing device, genetic algorithm, parallel hardware, random number generator, systolic array|
|Subjects:||University of Westminster > Science and Technology > Electronics and Computer Science, School of (No longer in use)|
|Depositing User:||Miss Nina Watts|
|Date Deposited:||27 Jan 2009 11:09|
|Last Modified:||19 Oct 2009 11:25|
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