Implementation of a block based neural branch predictor

Cadenas, Oswaldo and Megson, Graham M. and Jones, David J. (2005) Implementation of a block based neural branch predictor. In: 8th Euromicro Conference on Digital System Design: proceedings. IEEE, pp. 235-238. ISBN 0769524338

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Official URL: http://dx.doi.org/10.1109/DSD.2005.49

Abstract

This paper contributes to a dynamic branch predictor algorithm based on a perceptron in two directions: Firstly, a new block form of computation is introduced that reduces theoretically by half the combinational critical path for computing a prediction. Secondly, implementation in FPGA hardware is fully developed for quantitative comparison purposes. FPGA circuits for a one-cycle block predictor produces 1.7 faster clock rates than a direct implementation of the original perceptron predictor. This faster clock allows to realize predictions with longer history lengths for the same hardware budget.

Item Type: Book Section
Uncontrolled Keywords: Combinational circuits, field programmable gate arrays, perceptrons, FPGA hardware, block based neural branch predictor, dynamic branch predictor algorithm, perceptron predictor
Subjects: University of Westminster > Science and Technology > Electronics and Computer Science, School of (No longer in use)
Depositing User: Miss Nina Watts
Date Deposited: 27 Jan 2009 15:28
Last Modified: 19 Oct 2009 13:15
URI: http://westminsterresearch.wmin.ac.uk/id/eprint/5719

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