Cadenas, Oswaldo and Megson, Graham M. and Jones, David J. (2005) A new organization for a perceptron-based branch predictor and its FPGA implementation. In: Smailagic, Asim and Ranganathan, Nagarajan, (eds.) IEEE Computer Society annual symposium on VLSI: new frontiers in VLSI design. IEEE, Los Alamitos, USA, pp. 305-306. ISBN 076952365X
Full text not available from this repository.
Official URL: http://dx.doi.org/10.1109/ISVLSI.2005.11
An unaltered rearrangement of the original computation of a neural based predictor at the algorithmic level is introduced as a new organization. Its FPGA implementation generates circuits that are 1.7 faster than a direct implementation of the original algorithm. This faster clock rate allows to implement predictors with longer history lengths using the nearly the same hardware budget.
|Item Type:||Book Section|
|Uncontrolled Keywords:||Field programmable gate arrays, multilayer perceptrons predictor-corrector methods, FPGA, neural-based predictor computation, perceptron-based branch predictor, pipelined processors|
|Research Community:||University of Westminster > Electronics and Computer Science, School of|
|Deposited On:||27 Jan 2009 15:33|
|Last Modified:||19 Oct 2009 14:14|
Repository Staff Only: item control page