Cadenas, Oswaldo and Megson, Graham M. (2003) Power performance with gated clocks of a pipelined Cordic core. In: 5th International Conference on ASIC: proceedings. IEEE, pp. 1226-1230. ISBN 078037889XFull text not available from this repository.
This paper presents the evaluation in power consumption of gated clocks pipelined circuits with different register configurations in Virtex-based FPGA devices. Power impact of a gated clock circuitry aimed at reducing flip-flops output rate at the bit level is studied. Power performance is also given for pipeline stages based on the implementation of a double edge-triggered flip-flop. Using a pipelined Cordic core circuit as an example, this study did not find evidence in power benefits either when gated clock at the bit-level or double-edge triggered flip-flops are used when synthesized with FPGA logic resources.
|Item Type:||Book Section|
|Uncontrolled Keywords:||Field programmable gate arrays, flip-flops, pipeline arithmetic, power consumption, FPGA devices, FPGA logic double edge-triggered flip-flop, flip-flops, gated clock circuitry, gated clocks pipelined circuits, pipelined Cordic core, power consumption, power performance register configurations|
|Subjects:||University of Westminster > Science and Technology > Electronics and Computer Science, School of (No longer in use)|
|Depositing User:||Miss Nina Watts|
|Date Deposited:||27 Jan 2009 15:46|
|Last Modified:||19 Oct 2009 13:12|
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