Cadenas, Oswaldo and Megson, Graham M. (2003) Pullpipelining: a technique for systolic pipelined circuits. In: 3rd IEEE International workshop on system-on-chip for real-time applications. IEEE, pp. 205-210. ISBN 076951944X
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Pullpipelining, a pipeline technique where data is pulled from successor stages from predecessor stages is proposed. Control circuits using a synchronous, a semisynchronous and an asynchronous approach are given. Simulation examples for a DLX generic RISC datapath show that common control pipeline circuit overhead is avoided using the proposal. Applications to linear systolic arrays in cases when computation is finished at early stages in the array are foreseen. This would allow run-time data-driven digital frequency modulation of synchronous pipelined designs. This has applications to implement algorithms exhibiting average-case processing time using a synchronous approach.
|Item Type:||Book Section|
|Uncontrolled Keywords:||Data flow analysis, pipeline processing, reduced instruction set computing, systolic arrays, DLX generic RISC datapath, control circuit, linear systolic array, pipeline circuit overhead, predecessor stage, pullpipelining, reduced instruction set computing, run-time data-driven digital frequency modulation, successor stage, synchronous pipelined design, systolic pipelined circuit|
|Research Community:||University of Westminster > Electronics and Computer Science, School of|
|Deposited On:||27 Jan 2009 15:57|
|Last Modified:||19 Oct 2009 14:13|
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