Cadenas, Oswaldo and Megson, Graham M. (2001) Pipelining considerations for an FPGA case. In: Euromicro symposium on digital systems design: architectures, methods and tools. IEEE, pp. 276-283. ISBN 0769512399
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Official URL: http://dx.doi.org/10.1109/DSD.2001.952298
Abstract
This paper presents a semi-synchronous pipeline scheme, here referred as single-pulse pipeline, to the problem of mapping pipelined circuits to a Field Programmable Gate Array (FPGA). Area and timing considerations are given for a general case and later applied to a systolic circuit as illustration. The single-pulse pipeline can manage asynchronous worst-case data completion and it is evaluated against two chosen asynchronous pipelining: a four-phase bundle-data pipeline and a doubly-latched asynchronous pipeline. The semi-synchronous pipeline proposal takes less FPGA area and operates faster than the two selected fully-asynchronous schemes for an FPGA case.
| Item Type: | Book Section |
|---|---|
| Uncontrolled Keywords: | Field programmable gate arrays, logic design, timing, FPGA, asynchronous worst-case data completion, bundle-data pipeline, doubly-latched asynchronous pipeline, pipelining considerations, semi-synchronous pipeline scheme, single-pulse pipeline, systolic circuit, timing considerations |
| Research Community: | University of Westminster > Electronics and Computer Science, School of |
| ID Code: | 5727 |
| Deposited On: | 27 Jan 2009 16:15 |
| Last Modified: | 19 Oct 2009 14:12 |
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