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Transputer implementation of systolic arrays for model reduction

Megson, Graham M. (1988) Transputer implementation of systolic arrays for model reduction. In: IEE Colloquium on Recent Advances in Parallel Processing for Control. Institution of Electrical Engineers, London, 5/1-5/10.

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Official URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumbe...

Abstract

In control theory the dynamics representing a physical system to be controlled is analyzed in terms of a model built up from a mathematical description of the system components. Unfortunately the resulting model can have high or infinite dimensional state equations, so it is often necessary from a practical and computational viewpoint to find a reduced model of the system which mimics closely the behaviour of the high order system. The technique for producing these simplified descriptions is termed model reduction and a number of methods are known. The author is interested in applying computational parallelism to the generation of reduced models to provide an acceleration mechanism for use in a CAD environment. In the paper the author develops systolic algorithms for simple single input-output control problems and implements them on a network of transputers. The performance of this network is then evaluated with respect to a sequential algorithm for the same problems. Finally, the author points out that systolic arrays are normally considered as special purpose methods geared towards exploiting VLSI techniques.

Item Type:Book Section
Uncontrolled Keywords:CAD, control engineering computing, microprocessor chips, parallel processing, CAD environment, control engineering computing, model reduction, parallel processing, single input-output control problems, systolic arrays, transputers
Research Community:University of Westminster > Electronics and Computer Science, School of
ID Code:5744
Deposited On:28 Jan 2009 16:06
Last Modified:19 Oct 2009 16:40

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