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A clocking technique for FPGA pipelined designs

Cadenas, Oswaldo and Megson, Graham M. (2004) A clocking technique for FPGA pipelined designs. Journal of Systems Architecture, 51 (11). pp. 687-696. ISSN 1383-7621

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Official URL: http://dx.doi.org/10.1016/j.sysarc.2004.04.001

Abstract

This paper presents a clocking pipeline technique referred to as a single-pulse pipeline (PP-Pipeline) and applies it to the problem of mapping pipelined circuits to a Field Programmable Gate Array (FPGA). A PP-pipeline replicates the operation of asynchronous micropipelined control mechanisms using synchronous-orientated logic resources commonly found in FPGA devices. Consequently, circuits with an asynchronous-like pipeline operation can be efficiently synthesized using a synchronous design methodology. The technique can be extended to include data-completion circuitry to take advantage of variable data-completion processing time in synchronous pipelined designs. It is also shown that the PP-pipeline reduces the clock tree power consumption of pipelined circuits. These potential applications are demonstrated by post-synthesis simulation of FPGA circuits.

Item Type:Article
Research Community:University of Westminster > Electronics and Computer Science, School of
ID Code:5782
Deposited On:03 Feb 2009 10:15
Last Modified:19 Oct 2009 14:09

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