Systolic algorithms for B-spline patch generation

Megson, Graham M. (1991) Systolic algorithms for B-spline patch generation. Journal of Parallel and Distributed Computing, 11 (3). pp. 231-238. ISSN 0743-7315

Full text not available from this repository.
Official URL:


A systolic array for constructing the blending functions of B-spline curves and surfaces is described and shown to be 7k times faster than the equivalent sequential computation. The array requires just 5k inner product cell equivalents, where k ? 1 is the maximum degree of the blending function polynomials. This array is then used as a basis for a composite systolic architecture for generating single or multiple points on a B-spline curve or surface. The total hardware requirement is bounded by 5 max(k, l) + 3 (max(m, n) +1) inner product cells and O(mn) registers, where m and n are the numbers of control points in the two available directions. The hardware can be reduced to 5 max(k, l) + max(m, n) + 1 if each component of a point is generated by separate passes of data through the array. Equations for the array speed-up are given and likely speed-ups for different sized patches considered.

Item Type: Article
Subjects: University of Westminster > Science and Technology > Electronics and Computer Science, School of (No longer in use)
Depositing User: Miss Nina Watts
Date Deposited: 03 Feb 2009 10:45
Last Modified: 19 Oct 2009 15:29

Actions (login required)

Edit Item (Repository staff only) Edit Item (Repository staff only)