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Systolic algorithms for B-spline patch generation

Megson, Graham M. (1991) Systolic algorithms for B-spline patch generation. Journal of Parallel and Distributed Computing, 11 (3). pp. 231-238. ISSN 0743-7315

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Official URL: http://dx.doi.org/10.1016/0743-7315(91)90047-D


A systolic array for constructing the blending functions of B-spline curves and surfaces is described and shown to be 7k times faster than the equivalent sequential computation. The array requires just 5k inner product cell equivalents, where k − 1 is the maximum degree of the blending function polynomials. This array is then used as a basis for a composite systolic architecture for generating single or multiple points on a B-spline curve or surface. The total hardware requirement is bounded by 5 max(k, l) + 3 (max(m, n) +1) inner product cells and O(mn) registers, where m and n are the numbers of control points in the two available directions. The hardware can be reduced to 5 max(k, l) + max(m, n) + 1 if each component of a point is generated by separate passes of data through the array. Equations for the array speed-up are given and likely speed-ups for different sized patches considered.

Item Type:Article
Research Community:University of Westminster > Electronics and Computer Science, School of
ID Code:5787
Deposited On:03 Feb 2009 10:45
Last Modified:19 Oct 2009 16:29

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