Megson, Graham M. and Evans, David J. (1986) LISA: a parallel processing architecture. In: Händler, Wolfgang and Haupt, Dieter and Jeltsch, Rolf and Juling, Wilfried and Lange, Otto, (eds.) CONPAR 86: Conference on Algorithms and Hardware for Parallel Processing Aachen, September 17–19, 1986: proceedings. Lecture notes in computer science (237). Springer-Verlag, Berlin ; New York, pp. 361-375. ISBN 0387168117
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Official URL: http://dx.doi.org/10.1007/3-540-16811-7_191
The purpose of this paper is two-fold. Firstly, it introduces and develops the ideas of the Linear Instruction Systolic Array (LISA), and shows that it can simulate MIMD, SIMD and Systolic Wavefront Processor Algorithms involving nobacktracking. Secondly, we show that it can be used to develop a powerful Parallel Architecture based on LISA chips, which should be expandable and area efficient. As a subsidiary argument we can also demonstrate that there is real evidence for the role of Systolic Computation particularly pipelining in the development of parallel computations.
|Item Type:||Book Section|
|Research Community:||University of Westminster > Electronics and Computer Science, School of|
|Deposited On:||03 Feb 2009 11:34|
|Last Modified:||19 Oct 2009 16:51|
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