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A n-bit reconfigurable scalar quantiser

Cadenas, Oswaldo and Megson, Graham M. (2001) A n-bit reconfigurable scalar quantiser. In: Brebner, Gordon and Woods, Roger, (eds.) Field-Programmable Logic and Applications: 11th International Conference, FPL 2001 Belfast, Northern Ireland, UK, August 27-29, 2001: proceedings. Lecture notes in computer science (2147). Springer-Verlag, Berlin, pp. 420-429. ISBN 9783540424994

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Official URL: http://dx.doi.org/10.1007/3-540-44687-7_43

Abstract

A reconfigurable scalar quantiser capable of accepting n-bit input data is presented. The data length n can be varied in the range 1... N-1 under partial-run time reconfiguration, p-RTR. Issues as improvement in throughput using this reconfigurable quantiser of p-RTR against RTR for data of variable length are considered. The quantiser design referred to as the priority quantiser PQ is then compared against a direct design of the quantiser DIQ. It is then evaluated that for practical quantiser sizes, PQ shows better area usage when both are targeted onto the same FPGA. Other benefits are also identified.

Item Type:Book Section
Research Community:University of Westminster > Electronics and Computer Science, School of
ID Code:5795
Deposited On:03 Feb 2009 12:41
Last Modified:19 Oct 2009 14:10

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