Cadenas, Oswaldo and Megson, Graham M. (2002) A clocking technique with power savings in virtex-based pipelined designs. In: Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream: 12th International Conference, FPL 2002 Montpellier, France, September 2–4, 2002: proceedings. Lecture notes in computer science (2438). Springer-Verlag, Berlin, pp. 117-151. ISBN 9783540441083Full text not available from this repository.
This paper presents the evaluation in power consumption of a clocking technique for pipelined designs. The technique shows a dynamic power consumption saving of around 30% over a conventional global clocking mechanism. The results were obtained from a series of experiments of a systolic circuit implemented in Virtex-II devices. The conversion from a global-clocked pipelined design to the proposed technique is straightforward, preserving the original datapath design. The savings can be used immediately either as a power reduction benefit or to increase the frequency of operation of a design for the same power consumption.
|Item Type:||Book Section|
|Subjects:||University of Westminster > Science and Technology > Electronics and Computer Science, School of (No longer in use)|
|Depositing User:||Miss Nina Watts|
|Date Deposited:||03 Feb 2009 12:48|
|Last Modified:||19 Oct 2009 13:10|
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