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Design of a power-aware digital image rejection receiver

Cetin, Ediz and Kale, Izzet and Morling, Richard C.S. (2009) Design of a power-aware digital image rejection receiver. In: Proceedings of the IEEE International Symposium on Circuits and Systems, 2009 (ISCAS 2009). IEEE, pp. 209-212. ISBN 9781424438273

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Official URL: http://dx.doi.org/10.1109/ISCAS.2009.5117722

Abstract

This paper deals with and details the design of a power-aware adaptive digital image rejection receiver based on blind-source-separation that alleviates the RF analog front-end impairments. Power-aware system design at the RTL level without having to redesign arithmetic circuits is used to reduce the power consumption in nomadic devices. Power-aware multipliers with configurable precision are used to trade-off the image-rejection-ratio (IRR) performance with power consumption. Results of the simulation case studies demonstrate that the IRR performance of the power-aware system is comparable to that of the normal implementation albeit degraded slightly, but well within the acceptable limits.

Item Type:Book Section
Research Community:University of Westminster > Electronics and Computer Science, School of
ID Code:7401
Deposited On:28 Jan 2010 18:41
Last Modified:12 Aug 2010 10:09

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