Willingham, David J. and Kale, Izzet (2008) An asynchrobatic, radix-four, carry look-ahead adder. In: PRIME: 2008 PhD Research in Microelectronics and Electronics. Proceedings. Istanbul, Turkey, June 22–25, 2008. IEEE, pp. 105-108. ISBN 9781424419838
Official URL: http://dx.doi.org/10.1109/RME.2008.4595736
A low-power, Asynchrobatic (asynchronous, quasi-adiabatic), sixteen-bit, radix-four, parallel-prefix adder circuit is presented. The results show that it is an efficient, low power design, and that as would be expected with an asynchronous design, its performance is determined by its operating conditions. On a 0.35 mum CMOS process, under ldquotypicalrdquo process conditions, operating at an effective frequency of 22 MHz, an addition can be performed using 69 pW, with 48.3 pW used by the control logic and 20.7 pW by the data-path.
|Item Type:||Book Section|
|Research Community:||University of Westminster > Electronics and Computer Science, School of|
|Deposited On:||29 Jan 2010 11:09|
|Last Modified:||12 Aug 2010 10:09|
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