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A low-power asynchronous VLSI FIR filter

Bartlett, Viv A. and Grass, Eckhard (2001) A low-power asynchronous VLSI FIR filter. In: 19th Conference on Advanced Research in VLSI (ARVLSI 2001), 14-16 March 2001, Salt Lake City, UT, USA. IEEE Computer Society, Las Alamitos, USA, pp. 16-28. ISBN 076951037X

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Official URL: http://dx.doi.org/10.1109/ARVLSI.2001.915548

Abstract

An asynchronous FIR filter, based on a Single Bit-Plane architecture with a data-dependent, dynamic-logic implementation, is presented. Its energy consumption and sample computation delay are shown to correlate approximately linearly with the total number of ones in its coeflcient-set. The proposed architecture has the property that coefficients in a Sign-Magnitude representation can be handled at negligible overhead which, for typical filter coefficient-sets, is shown to offer significant benefits to both energy consumption and throughput. Transistor level simulations show energy consumption to be lower than in previously reported designs.

Item Type:Book Section
Research Community:University of Westminster > Electronics and Computer Science, School of
ID Code:901
Deposited On:01 Dec 2005
Last Modified:11 Aug 2010 15:29

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