Using carry-save adders in low-power multiplier blocks

Bartlett, Viv A. and Dempster, Andrew G. (2001) Using carry-save adders in low-power multiplier blocks. In: IEEE International Symposium on Circuits and Systems (ISCAS), 2001. IEEE Computer Society, Las Alamitos, USA, pp. 222-225. ISBN 0780366859

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Official URL: http://dx.doi.org/10.1109/ISCAS.2001.922212

Abstract

For a simple multiplier block FIR filter design, we compare the effects on power consumption of using direct versus transposed direct forms, tree versus linear structures and carry-save (CS) versus carry-ripple (CR) adders (for which multiplier block algorithms have been designed). We find that tree structures offer power savings, as expected, as does transposition in general but not always. Selective use of CS adders is shown to offer power savings provided that care is taken with their deployment. Our best result is with a direct form CWCS hybrid. The need for new multiplier-block design algorithms is identified.

Item Type: Book Section
Subjects: University of Westminster > Science and Technology > Electronics and Computer Science, School of (No longer in use)
Depositing User: Users 4 not found.
Date Deposited: 01 Dec 2005
Last Modified: 11 Aug 2010 14:29
URI: http://westminsterresearch.wmin.ac.uk/id/eprint/903

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