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Design guidelines for reconfigurable multiplier blocks

Demirsoy, Suleyman S. and Dempster, Andrew G. and Kale, Izzet (2003) Design guidelines for reconfigurable multiplier blocks. In: 2003 IEEE International Symposium on Circuits and Systems. IEEE Computer Society, Las Alamitos, USA, pp. 293-296. ISBN 0780377613

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Official URL: http://dx.doi.org/10.1109/ISCAS.2003.1205831

Abstract

The newly proposed reconfigurable multiplier blocks offer significant savings in area over the traditional multiplier blocks for time-multiplexed digital filters or any other system where only a subset of the coefficients that can be produced by the multiplier block is needed in a given time. The basic structure comprises a multiplexer connected to at least one input of an adder/subtractor that can generate several partial products, leading to better area utilization. The multiplier block algorithm complexity of a design increases logarithmically as the number of the multiplexers is increased. Design guidelines for the maximum utilization of the reconfigurable multiplier block structures are also presented.

Item Type:Book Section
Research Community:University of Westminster > Electronics and Computer Science, School of
ID Code:959
Deposited On:01 Dec 2005
Last Modified:11 Aug 2010 15:29

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