Design guidelines for reconfigurable multiplier blocks

Demirsoy, Suleyman S., Dempster, Andrew G. and Kale, Izzet (2003) Design guidelines for reconfigurable multiplier blocks. In: 2003 IEEE International Symposium on Circuits and Systems. IEEE Computer Society, Las Alamitos, USA, pp. 293-296. ISBN 0780377613


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The newly proposed reconfigurable multiplier blocks offer significant savings in area over the traditional multiplier blocks for time-multiplexed digital filters or any other system where only a subset of the coefficients that can be produced by the multiplier block is needed in a given time. The basic structure comprises a multiplexer connected to at least one input of an adder/subtractor that can generate several partial products, leading to better area utilization. The multiplier block algorithm complexity of a design increases logarithmically as the number of the multiplexers is increased. Design guidelines for the maximum utilization of the reconfigurable multiplier block structures are also presented.

Item Type: Book Section
Subjects: University of Westminster > Science and Technology > Electronics and Computer Science, School of (No longer in use)
Depositing User: Users 4 not found.
Date Deposited: 01 Dec 2005
Last Modified: 11 Aug 2010 14:29

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