Designing multiplier blocks with low logic depth

Dempster, Andrew G. and Demirsoy, Suleyman S. and Kale, Izzet (2002) Designing multiplier blocks with low logic depth. In: IEEE ISCAS International Symposium on Circuits and Systems. IEEE Computer Society, USA, pp. 773-776. ISBN 0780374487

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Official URL: http://dx.doi.org/10.1109/ISCAS.2002.1010818

Abstract

The depth of logic in an integrated circuit, particularly a CMOS circuit, is highly correlated both with power consumption and degraded switching speed. Hence, designs with low logic depth can aid in reducing power consumption and increasing switching speed. In this paper we demonstrate how new and modified algorithms have been used to design multiplier blocks with low logic depth and power consumption.

Item Type: Book Section
Subjects: University of Westminster > Science and Technology > Electronics and Computer Science, School of (No longer in use)
Depositing User: Users 4 not found.
Date Deposited: 01 Dec 2005
Last Modified: 11 Aug 2010 14:29
URI: http://westminsterresearch.wmin.ac.uk/id/eprint/960

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