Demirsoy, Suleyman S. and Dempster, Andrew G. and Kale, Izzet (2005) Efficient implementation of digital filters using novel reconfiguaration multiplier blocks (REMB). In: Conference record of the Thirty-Eighth Asilomar Conference on Signals, Systems and Computers, 2004: November 7-10, 2004, Pacific Grove, California. IEEE Computer Society, Piscataway, N.J., USA, pp. 461-464. ISBN 0780386221
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Official URL: http://dx.doi.org/10.1109/ACSSC.2004.1399175
Abstract
Reconfigurable Multiplier Blocks (ReMB) offer significant complexity reductions in multiple constant multiplications in time-multiplexed digital filters. In this paper the ReMB technique is employed in the implementation of a half-band 32-tap FIR filter on both Xilinx Virtex FPGA and UMC 0.18micro m CMOS technologies. Reference designs have also been built by deploying standard time-multiplexed architectures and off-the-shelf Xilinx Core Generator system for the FPGA design. All designs are then compared for their area and delay figures. It is shown that, the ReMB technique can significantly reduce the area for the multiplier circuitry and the coefficient store, as well as reducing the delay.
| Item Type: | Book Section |
|---|---|
| Research Community: | University of Westminster > Electronics and Computer Science, School of |
| ID Code: | 961 |
| Deposited On: | 01 Dec 2005 |
| Last Modified: | 11 Aug 2010 15:29 |
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