Power analysis of multiplier blocks

Demirsoy, Suleyman S. and Dempster, Andrew G. and Kale, Izzet (2002) Power analysis of multiplier blocks. In: IEEE ISCAS International Symposium on Circuits & Systems. IEEE Computer Society, USA, pp. 297-300. ISBN 0780374487

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Official URL: http://dx.doi.org/10.1109/ISCAS.2002.1009836

Abstract

In this study, three multiplier-blocks generated by different algorithms are analyzed for their power consumption via transition count based on their implementation on the Xilinx Virtex device. The high level Glitch-Path method, which is used for estimating the relative figures of transitions occurring at the outputs of the adders, has been refined for more accurate estimation and a new method GP Score is proposed. Several design issues are discussed regarding ways of reducing the transitions.

Item Type: Book Section
Subjects: University of Westminster > Science and Technology > Electronics and Computer Science, School of (No longer in use)
Depositing User: Users 4 not found.
Date Deposited: 01 Dec 2005
Last Modified: 11 Aug 2010 14:29
URI: http://westminsterresearch.wmin.ac.uk/id/eprint/963

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