Demirsoy, Suleyman S. and Dempster, Andrew G. and Kale, Izzet (2002) Power consumption behaviour of multiplier block algorithms. In: Proceedings of the 2002 45th Midwest Symposium on Circuits and Systems. IEEE Computer Society, Las Alamitos, USA, pp. 1-4. ISBN 0780375238
Multiplier blocks have been used primarily for the reduction of circuit complexity. Using new algorithms, it has been shown that they can also be used for effective reduction of power consumption in digital filter circuits. In this paper, the new GP score method is used as a relative power measure to compare digital filter multiplier blocks using the BHM, RAGn and CI algorithms.
|Item Type:||Book Section|
|Research Community:||University of Westminster > Electronics and Computer Science, School of|
|Deposited On:||01 Dec 2005|
|Last Modified:||11 Aug 2010 15:29|
Repository Staff Only: item control page