Demirsoy, Suleyman S. and Kale, Izzet and Dempster, Andrew G. (2005) Synthesis of reconfigurable multiplier blocks: part II: algorithm. In: IEEE International Symposium on Circuits and Systems 2005. IEEE Computer Society, Piscataway, N.J., USA, pp. 540-543. ISBN 0780388348
![[img]](http://westminsterresearch.wmin.ac.uk/style/images/fileicons/application_pdf.png)
| PDF 350Kb |
Official URL: http://dx.doi.org/10.1109/ISCAS.2005.1464644
Abstract
Reconfigurable Multiplier Blocks (ReMB) offer significant area, delay and possibly power reduction in time-multiplexed implementation of multiple constant multiplications. This paper and its companion paper (entitled Part I- Fundamentals) together present a systematic synthesis method for Single Input Single Output (SISO) and Single Input Multiple Output (SIMO) ReMB designs. This paper illustrates the synthesis method through examples. The companion paper presents the necessary foundation and terminology needed for developing a systematic synthesis technique. The proposed method achieves reduced logic-depth and area over standard multipliers / multiplier blocks.
| Item Type: | Book Section |
|---|---|
| Research Community: | University of Westminster > Electronics and Computer Science, School of |
| ID Code: | 967 |
| Deposited On: | 01 Dec 2005 |
| Last Modified: | 11 Aug 2010 15:29 |
Repository Staff Only: item control page
