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Items where Author is Cadenas, Oswaldo

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Number of items: 20.

2006

Cadenas, Oswaldo and Megson, Graham M. (2006) Verification and FPGA circuits of a block-2 fast path-based predictor. In: International Conference on Field Programmable Logic and Applications, Madrid, Spain, 28-30 Aug. 2006. FPL '06. IEEE, pp. 213-218. ISBN 142440312X

Cadenas, Oswaldo and Megson, Graham M. (2006) FPGA organisation of a block-2 fast path-based predictor. In: FPL06: 16th International Conference on Field Programmable Logic and Applications, 28-30 August 2006, Meliá Madrid Princesa, Madrid, Spain. (Submitted)

2005

Cadenas, Oswaldo and Megson, Graham M. and Jones, David J. (2005) FPGA organization for the fast path-based neural branch predictor. In: 2005 IEEE International Conference on Field-Programmable Technology, National University of Singapore, Singapore, 11-14 Dec 2008: proceedings. IEEE, pp. 251-257. ISBN 0780394070

Cadenas, Oswaldo and Megson, Graham M. and Jones, David J. (2005) Implementation of a block based neural branch predictor. In: 8th Euromicro Conference on Digital System Design: proceedings. IEEE, pp. 235-238. ISBN 0769524338

Cadenas, Oswaldo and Megson, Graham M. and Jones, David J. (2005) A new organization for a perceptron-based branch predictor and its FPGA implementation. In: Smailagic, Asim and Ranganathan, Nagarajan, (eds.) IEEE Computer Society annual symposium on VLSI: new frontiers in VLSI design. IEEE, Los Alamitos, USA, pp. 305-306. ISBN 076952365X

2004

Cadenas, Oswaldo and Megson, Graham M. (2004) Fractal quantization. In: 2004 IEEE International Symposium on Consumer Electronics: proceedings: September 1-3 2004. IEEE, Piscataway, N.J., pp. 461-464. ISBN 0780385276

Cadenas, Oswaldo and Brandt, Mark-Alexander and Megson, Graham M. and Goswami, Nomita (2004) Investigation into low power of a 2D inverse discrete cosine transform (IDCT) in FPGAs. In: 2004 IEEE International Symposium on Consumer Electronics: proceedings: September 1-3 2004. IEEE, Piscataway, N.J., pp. 465-469. ISBN 0780385276

Cadenas, Oswaldo and Megson, Graham M. (2004) A clocking technique for FPGA pipelined designs. Journal of Systems Architecture, 51 (11). pp. 687-696. ISSN 1383-7621

Cadenas, Oswaldo and Megson, Graham M. (2004) A FPGA pipelined backward adaptive scalar quantizer. In: Proceedings of the Second IASTED International Conference on Circuits, Signals, and Systems, Clearwater Beach, FL, USA, November 28 - December 1, 2004. IASTED/ACTA Press, pp. 410-415.

2003

Cadenas, Oswaldo and Megson, Graham M. (2003) Power performance with gated clocks of a pipelined Cordic core. In: 5th International Conference on ASIC: proceedings. IEEE, pp. 1226-1230. ISBN 078037889X

Cadenas, Oswaldo and Megson, Graham M. (2003) Pullpipelining: a technique for systolic pipelined circuits. In: 3rd IEEE International workshop on system-on-chip for real-time applications. IEEE, pp. 205-210. ISBN 076951944X

Cadenas, Oswaldo and Megson, Graham M. and Plaks, Toomas P. (2003) FPGA circuits for a Monte-Carlo based matrix inversion architecture. In: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, June 23 - 26, 2003, Las Vegas, Nevada, USA. CSREA Press, pp. 201-217. ISBN 193241505X

Cadenas, Oswaldo and Megson, Graham M. (2003) An average-case classifier algorithm and FPGA implementation. In: Rashid, Muhammad Harunur, (ed.) Circuits, signals, and systems: proceedings of the IASTED international conference on circuits, signals, and systems. May 19-21 2003, Cancun, Mexico. Acta Press, pp. 285-289. ISBN 9780889863514

Plaks, Toomas P. and Megson, Graham M. and Cadenas, Oswaldo and Alexandrov, Vassil N. (2003) A linear algebra processor using Monte Carlo methods. In: 2003 MAPLD International Conference, 09 - 13 Dec 2003, Ronald Reagan Building and International Trade Center, Washington D.C..

2002

Cadenas, Oswaldo and Megson, Graham M. (2002) Improving mW/MHz ratio in FPGAs pipelined designs. In: Edwards, Martyn, (ed.) Euromicro symposium on digital system design: architectures, methods and tools: proccedings. IEEE, pp. 276-282. ISBN 0769517900

Cadenas, Oswaldo and Megson, Graham M. (2002) A clocking technique with power savings in virtex-based pipelined designs. In: Glesner, Manfred and Zipf, Peter and Renovell, Michel, (eds.) Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream: 12th International Conference, FPL 2002 Montpellier, France, September 2–4, 2002: proceedings. Lecture notes in computer science (2438). Springer-Verlag, Berlin, pp. 117-151. ISBN 9783540441083

2001

Cadenas, Oswaldo and Megson, Graham M. (2001) Pipelining considerations for an FPGA case. In: Euromicro symposium on digital systems design: architectures, methods and tools. IEEE, pp. 276-283. ISBN 0769512399

Cadenas, Oswaldo and Megson, Graham M. (2001) A n-bit reconfigurable scalar quantiser. In: Brebner, Gordon and Woods, Roger, (eds.) Field-Programmable Logic and Applications: 11th International Conference, FPL 2001 Belfast, Northern Ireland, UK, August 27-29, 2001: proceedings. Lecture notes in computer science (2147). Springer-Verlag, Berlin, pp. 420-429. ISBN 9783540424994

2000

Cadenas, Oswaldo and Megson, Graham M. and Plaks, Toomas P. (2000) Accelerating JPEG compression with a dynamically reconfigurable FPGA systolic array. In: International Conference on Parallel and Distibuted Processing Techniques and Applications, vol VI, 26 - 29 June 2000, Las Vegas, USA. (Submitted)

1999

Plaks, Toomas P. and Cadenas, Oswaldo and Megson, Graham M. (1999) Experiences using reconfigurable FPGAs in implementing Monte-Carlo methods. In: Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 1999, June 28 - Junlly 1, 1999, Las Vegas, Nevada, USA. CSREA Press, pp. 1131-1137. ISBN 1892512157

This list was generated on Tue Nov 25 20:37:48 2014 GMT.